ARM's Artisan Physical IP embedded memory compiler portfolio includes Single Port SRAM, Single Port Register File, Dual Port SRAM, Two Port Register File, and ROM functionality, and offers IC designers a wide range of choices. The high-performance, high-density, low-power and ultra low-power memory compilers are optimized for each silicon technology. Each compiler is delivered with a complete set of views and models for leading EDA tools. Browse the ARM Physical IP Product Catalog to view the memory compiler and other products available for a particular foundry and process. The ARM Process-Perfect™ Design Methodology includes comprehensive QA and validation procedures that can enable accurate designs with high manufacturing yields.
The memory compiler features and benefits are listed below:- | Features | Benefits | - Broadly configurable up to 512Kbits
- Optional Flex-Repair™ Redundancy
- Aspect ratio control
- Programmable mask write of 1-36 bits
- Speed, power and speed/density optimized architectures
- Low active power and leakage only standby power
- Extensive EDA view support
| - Economically integrates small and multi-megabit memories
- Floorplanning flexibility
- Mix and match architectures on the same chip to optimize your design
- Minimized power reduces design complexity and package cost
- Easy integration into complete design using EDA views
|
| Features | Benefits | - Broadly configurable up to 256Kbits
- Aspect ratio control
- Two independent read/write ports
- Programmable mask write of 1-36 bits
- Speed/density and power optimized architectures
- Low active power and leakage only standby power
- Extensive EDA view support
| - Economically integrates small and multi-megabit memories
- Floorplanning flexibility
- Mix and match architectures on the same chip to optimize your design
- Minimized power reduces design complexity and package cost
- Easy integration into complete design using EDA views
|
| Features | Benefits | - Broadly configurable up to 32Kbits
- Same bitcell as single-port SRAM
- Aspect Ratio control
- Programmable mask write of 1-36 bits
- Speed/density and power optimized architectures
- Low active power and leakage only standby power
- Extensive EDA view support
| - Optimized solution for low-capacity memory
- Floorplanning flexibility
- Mix and match architectures on the same chip to optimize your design
- Minimal power reduces design complexity and package cost
- Easy integration into complete design using EDA views
|
| Features | Benefits | - Broadly configurable up to 16Kbits
- Same bitcell as dual port SRAM
- One dedicated read port & one dedicated write port
- Aspect ratio control
- Programmable mask write of 1-36 bits
- Speed/density and density optimized architectures
- Low-active power and leakage only standby power
- Extensive EDA view support
| - Optimized solution for low-capacity two-port memory requirements
- Floorplanning flexibility
- Mix and match architectures on the same chip to optimize your design
- Minimized power reduces design complexity and package cost
- Easy integration into complete design using EDA views
|
| Features | Benefits | - Broadly configurable up to 2Mbits
- Diffusion-mask or via-mask programmable
- Aspect ratio control
- Speed/density and density optimized architectures
- Low active power and leakage only standby power
- Extensive EDA view support
| - Floorplanning flexibility
- Minimal power reduces design complexity and package cost
- Easy integration into complete design using EDA views
|
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