The ARM® emBISTRx™ embedded memory and test repair system is an integrated BIST/BISR solution that is tightly coupled to the ARM Advantage™ and Metro™ memory compilers. This integrated test and repair approach delivers the most optimal die yield for SoC designs and the highest test quality with minimum design impact. The BIST/BISR technology offers algorithmic flexibility to achieve high defect coverage, especially for sub-nanometer defects, and optimal reparability tuned to memory specific redundancy architecture. The memory sub-system architecture leverages the open standard IEEE 1500 to communicate with chip-level test ports and facilitates manufacturing test and repair. The emBISTRx™ system provides automation for quick implementation of the embedded memory sub-system for Advantage and Metro memories with test and repair. This process allows the designer to quickly and easily integrate into a high-level design flow to support synthesis and verification tools. Based on a hierarchical distributed architecture the emBISTRx system simplifies the overall complexity of implementing embedded memory sub-system and drastically reduces the wiring (routing) congestion The architecture is flexible and can easily support hundreds of memories per controller and allows for various modes of test and repair including silicon bring-up, manufacturing test, system level test, field test, maintenance and failure analysis.
 emBISTRx System
BRC: BIST& Repair Controller
WR: Smart Wrapper
J2P: Chip level test interface
FC: Fuse Controller
| Features | Benefits | - Hierarchically distributed test & repair architecture
- Advanced test algorithms targeting real-world defects with at-speed test capability
- Flexible repair strategy ( Hard, Soft, cumulative) to achieve optimum reparability
- Test & Repair system tightly integrated to the memory architecture
- Automation to integrate test & repair system into SoC design
| - Simplifies design complexity and drastic reduction in wiring congestion
- Highest test quality to achieve lower DPM (defective parts shipped per million) and reduce field returns
- Increased die yield leading to higher profit margins
- Minimal design impact makes timing closure and sub-system construction easier
- Enhanced design productivity, cuts down overall design cycle time and accelerates time-to-market
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