ARM® develops Silicon On Insulator (SOI) Physical IP products based on SOI CMOS technology and tuned to the processes of its foundry partners. IP design is developed using proprietary SOI design techniques and characterization tools, and a methodology that enables SoC designers to transparently integrate SOI IP in their standard ASIC/COT design flow. This transparency is enabled by compatibility with standard EDA design flows with no requirement for specialist SOI knowledge. SOI Physical IP allows designers to fully utilize the benefits of SOI to exceed the performance and power consumption benchmarks the industry demands. SOI technology offers a different set of benefits to a traditional CMOS process. With the right optimization, specific applications can benefit from: - 30-40% speed improvement
- Up to 50% reduction in dynamic power consumption
- Up to 10% area reduction
This is achieved using ARM SOI-specific patented IP, patented characterization methodology and proprietary architectures.
ARM Physical IP Silicon On Insulator (SOI) Portfolio Standard Cell Library - SOI standard cell library, supporting multiple Vts
- Multi-Vdd characterization
- SOI power management kit
GP I/O Library - SOI general-purpose IO
- Input tolerant GPIO
Memory - SOI single-port SRAM
- SOI dual-port SRAM
- SOI single-port Register files
- SOI two-port register files
- SOI programmable ROM
Tools and Expertise - SOI specific IP architectures and design
- Proprietary SOI characterization methodology and tools
- Proprietary and patented cells, architectures and flows
- IP optimization to achieve 100% SOI benefits
- SOI specificities transparent to designer
- No SOI training needed
- Extensive validation/qualification
- Know-how based on numerous SOI tape-outs down to 65nm
Quality Assessment
ARM offers a tightly controlled development and qualification flow from specifications to silicon qualification to provide high-quality libraries. Silicon Qualification Test Chips
A set of test chips is designed for complete qualification and validation of all Physical IP. Customer Design Flow
The ARM SOI Physical IP is designed for use in standard EDA design flows and by non SOI experts Deliverables
The list of EDA views delivery for standard cells, I/O and memory compilers is available upon request.
For more information about the technologies supported by ARM and the corresponding libraries, please contact us. | 
