For a highly differentiated consumer electronics product to succeed, electronics vendors need a way to perform very early testing and verification of hardware and software integration, early verification of the user experience, and early content generation for the end product. To achieve this, software developers need a target early in the design cycle that is representative of the final system, easy to deploy, and which engineers can interact with in real time to design and test their software. The RealView System Generator tool enables engineers to generate instruction-accurate fast virtual prototypes themselves that are scaleable, reusable, and allow the parallel development of software and hardware. These prototypes are fast enough to be used interactively to test applications in real time. The virtual prototypes generated by the RealView System Generator tool are based around the only certified high-speed models of ARM IP, including the TrustZone® hardware-based security technology and Jazelle® Java acceleration technology. A number of pre-configured system models are also available. Known as Real Time System Models (or RTSMs), these are based on the Integrator/CP or Emulation Baseboard hardware platforms. System Generator allows you to expand and modify any of these example systems. The System Generator Tool.
 
An example generated model and debugger.
- Easy to use drag-and-drop user interface generates very fast custom prototypes of ARM processor-based platforms
- Real-time testing of application software
- Library of very fast processor models and peripherals
- Enables content development not previously possible using instruction set simulators
- Code running on virtual prototypes can be easily debugged using RealView tools or third-party tools
- Generated models can be deployed to development teams
- Support for multiple processor cores in a system model
- Upper middleware and application software developers
- Mobile game developers
- Mobile commerce and security application developers
- Java application developers
The System Generator tool is used to construct a virtual platform from a library of processor and peripheral models through a block-based graphical user interface, or design canvas. User models can be imported and the model sources edited and system parameters configured.
When the design is complete, the user presses a button to check the design, for example to ensure the behaviours of connected components are compatible. The user then presses another button to generate the model. The generated model does not require the System Generator tool to run. It is a stand-alone executable or shared library that can be loaded into a software debugger, such as the Model Debugger or RealView Debugger. Library of ARM processor models - ARM968E-S™
- ARM926EJ-S™
- ARM1136JF-S™
- ARM1176JZF-S™
- Cortex™-R4
- Cortex™-A8
- Cortex™-A9 and PL310 L2 cache controller
- and a roadmap including ARM11 MPCore™ and Cortex™-M3
Library of PrimeCell peripherals including, - PL011 UART
- PL022 Synchronous Serial Device
- PL030 Real-time Clock
- PL041 Audio Codec Interface
- PL050 Keyboard and Mouse Interface
- PL061 GPIO
- PL080 DMA Controller
- PL110/111 Color LCD Controllers
- PL180 Multi-media Card Interface
- PL192 Vectored Interrupt Controller
- PL340 Dynamic Memory Controller
- PL350 Static Memory Controller
- Various TrustZone components
Library of other peripherals, many of which are provided in source form, including - Virtual file system
- UARTs
- Timers
- Interrupt controllers
- Ethernet
- NAND and NOR flash
- MMC cards
- Bus decoders
- Generic components like LEDs and switches
Benchmark system: Pentium-M, 1.7GHz, 1GB RAM, running Linux under VMware Operation | Demonstrates | Measured | Dual-core Linux boot: u-boot + 2.6.14 kernel + 9MB ROMFS | Realistic scenario | 7s or ~128M i/s (~64M per core) | Both cores idle at Linux prompt | Peak performance | ~570M i/s (285M per core) | Both cores executing ‘ls –ltR’ | Repeated I/O | ~152M i/s (76M per core) | Both cores executing gzip / gzip –d on a file in RAMFS | Compute-bound | ~124M i/s (62M per core) | One core idle, other core gzip / gzip –d on file in RAMFS | Asymmetric load | ~200M i/s (100M per core) |
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